Tentative Schedule
High End Workshop on AI/ML Algorithms and Applications in VLSI Design and Technology
(Under the KARYASHALA Scheme – A SERB initiative)
17th – 22nd July 2023
The schedule can be downloaded from here
-
08:30 am to 09:00 am
Registration (AIP Lab, Lab
Building,
Ground Floor)
-
09:00 am to 09:45 am
Inauguration (AIP Lab, Lab
Building,
Ground Floor)
-
09:45 am – 10:15 am
High Tea
-
Slot-1 -> 10:15am – 11:30 am
Applying Computational
Intelligence and Machine
Learning to address
Computational Problems in
VLSI Systems
(Dr. Jai Narayan Tripathi,
IIT Jodhpur)
-
Slot-2 -> 11:45 am to 01:00 pm
Applying Computational
Intelligence and Machine
Learning to address
Computational Problems in
VLSI Systems
(Dr. Jai Narayan Tripathi,
IIT Jodhpur)
-
01:00 pm to 2:00 pm
Lunch
-
Slot-3 -> 2:00 pm to 5:00 pm
Lab on Computational
Intelligence and Machine
Learning in VLSI
(Dr. Jai Narayan Tripathi,
IIT Jodhpur)
-
Slot-1 -> 10:00am – 11:15 am
Machine Learning and
Overview
(Dr. M. V. Joshi,
DA-IICT Gandhinagar)
-
11:15 am – 11:30 am
Tea & Snacks
-
Slot-2 -> 11:30 am to 12:45 pm
Deep Learning:
Conceptual and Practical
Guide
(Dr. Bakul Gohel,
DA-IICT Gandhinagar)
-
12:45 pm to 2:00 pm
Lunch
-
Slot-3 -> 2:00 pm to 3:30 pm
Lab on Machine Learning
and Deep Learning
(Dr. M.V. Joshi and Dr. Bakul,
DA-IICT Gandhinagar)
-
03:30 pm – 03:45 pm
Tea & Snacks
-
Slot-4 -> 03:45 pm to 5:00 pm
Lab on Machine Learning
and Deep Learning
(Dr. M.V. Joshi and Dr. Bakul,
DA-IICT Gandhinagar)
-
Slot-1 -> 10:00am – 11:15 am
Applications of AI/ML in
Embedded and VLSI Design
(Dr. Vinay Palaparthy,
DA-IICT Gandhinagar)
-
11:15 am – 11:30 am
Tea & Snacks
-
Slot-2 -> 11:30am – 12:45 am
Applications of AI/ML in
Embedded and VLSI Design
(Dr. Vinay Palaparthy,
DA-IICT Gandhinagar)
-
12:45 pm to 2:00 pm
Lunch
-
Slot-3 -> 2:00 pm to 3:30 pm
Lab on Exploratory Data
Analysis
(Dr. Vinay Palaparthy,
DA-IICT Gandhinagar)
-
03:30 pm – 03:45 pm
Tea & Snacks
-
Slot-4 -> 03:45 pm to 5:00 pm
Lab on Exploratory Data
Analysis
(Dr. Vinay Palaparthy,
DA-IICT Gandhinagar)
-
Slot-1 -> 10:00am – 11:15 am
Hardware Design for AI/ML
(Dr. Binod Kumar,
IIT Jodhpur)
-
11:15 am – 11:30 am
Tea & Snacks
-
Slot-2 -> 11:30 am to 12:45 pm
Hardware Design for
AI/ML
(Dr. Binod Kumar,
IIT Jodhpur)
-
12:45 pm to 2:00 pm
Lunch
-
Slot-3 -> 2:00 pm to 3:30 pm
Hardware Design
Implementation of AI/ML
Applications
(Dr. Binod Kumar,
IIT Jodhpur)
-
03:30 pm – 03:45 pm
Tea & Snacks
-
Slot-4 -> 03:45 pm to 5:00 pm
Hardware Design
Implementation of AI/ML
Applications
(Dr. Binod Kumar,
IIT Jodhpur)
-
Slot-1 -> 10:00am – 11:15 am
Machine Learning based
Analysis of VLSI Signal and
Power Integrity Challenges
(Dr. Kavicharan Mummaneni,
NIT Silchar)
-
11:15 am – 11:30 am
Tea & Snacks
-
Slot-2 -> 11:30 am to 12:45 pm
Machine Learning based
Analysis of VLSI Signal and
Power Integrity Challenges
(Dr. Kavicharan Mummaneni,
NIT Silchar)
-
12:45 pm to 2:00 pm
Lunch
-
Slot-3 -> 2:00 pm to 3:30 pm
VLSI and on-chip
Interconnect System
(Dr. Yash Agrawal,
DA-IICT Gandhinagar)
-
03:30 pm – 03:45 pm
Tea & Snacks
-
Slot-4 -> 4:00 pm to 5:00 pm
Lab on VLSI Interconnect
System Design using
AI/ML
(Dr. Yash Agrawal,
DA-IICT Gandhinagar)